Design and implementation of Low-Power Network-on-Chip for Application to High-Performance System-on-Chip Design Design and implementation of Low-Power Network-on-Chip for Application to High-Performance System-on-Chip Design

A low-power packet-switched Network-on-Chip (NoC) is designed with hierarchical star topology and implemented in real silicon for possible application to high-performance SoCs. This dissertation presents how to obtain low power consumption in NoC while the whole NoC design process is covered from the architecture decision to the system demonstration. First, a performance and cost oriented topology exploration is performed. The evaluated topologies include not only flat topologies such as a bus, mesh, star and point-to-point but also sixteen hierarchical and heterogeneous topologies. The evaluation method uses technology-independent analytical models with implementation-based physical parameters. Second, the detail network architecture such as switching method, packet synchronization, link serialization, protocol and buffering schemes are analyzed with special emphasis on low power consumption. The implemented chip contains